Accurately solve microstrip & stripline trace geometries from real-world PCB factory stackups. Features high-speed protocol quick-picker, one-click Altium/KiCad rule export, and direct quote order bridge.
No impedance requirements added yet. Click '+ Add to Impedance Design Table' above to create records.
Our solver combines IPC-2141A and Wadell closed-form electromagnetic field equations with 608+ verified 4L–32L PCBPath factory press stackups (including pressed 1080/2116/7628 prepreg thicknesses, core heights, copper weights, and dielectric constants Dk). Select your layer count and target impedance to instantaneously back-solve manufacturable trace width (W) and differential spacing (S).
Use Single-Ended or Edge-Coupled Differential Microstrip for outer layers (Top L1 / Bottom Ln) referenced to a single adjacent ground plane. Use Symmetric or Asymmetric Stripline for inner signal layers sandwiched between two reference planes—ideal for low-crosstalk PCIe and DDR routing. Use Grounded Coplanar Waveguide (CPWG) when routing 50Ω RF traces surrounded by same-layer ground pour and via stitching.
Industry-standard characteristic impedances are: USB 2.0 at 90Ω differential; USB 3.x, PCIe Gen3/4/5, and DDR3/4/5 DQS at 85Ω differential; HDMI 2.0/2.1, 1G/10G Ethernet, and LVDS at 100Ω differential; CAN Bus and RS-485 at 120Ω differential; and RF antenna feeds / DDR single-ended clocks at 50Ω single-ended. You can load any of these with 1 click using the Protocol Quick-Picker above.
During multilayer lamination, resin from prepreg plies (such as 1080, 2116, or 7628) flows into adjacent inner-layer copper clearances, reducing final dielectric height by 10–30 µm and shifting effective Dk between 3.8 and 4.6 depending on glass-to-resin ratio. Designing directly on PCBPath's verified pressed stackup templates prevents CAM engineering holds (EQ) and trace-width adjustments after ordering.
Click '+ Add to Impedance Design Table' to save your solved signal layers, then use the 'Export Altium (.rul)' or 'Export KiCad Rules' buttons to import trace width and clearance constraints straight into your EDA layout tool. When ready to fabricate, click 'Apply to Quote' to transfer your stackup code and full impedance table into the PCB quote page with zero manual re-entry.
Every controlled-impedance PCB order includes dedicated production test coupons on the fabrication panel and 100% Time-Domain Reflectometry (TDR) inspection. Our standard impedance tolerance is ±10% (±5Ω for ≤50Ω single-ended traces), with tight ±5% precision tolerance available for high-speed RF and Advanced HDI boards.
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